1. Field of the Invention
The present invention relates to a semiconductor memory device which allows non-destructive reading, and in particular, to a semiconductor memory device which can decrease the total coupling capacitance between the bit lines, and which can accelerate the operation for reading data.
2. Description of the Related Art
As micro-processing technology develops, the pitch width between the bit lines used to read or write data in a semiconductor memory device is decreased. Therefore, the coupling capacitance between the bit lines is increased as the memory cell area becomes small.
To explain the coupling capacitance, the arrangement of the bit lines in a conventional static random access memory (SRAM) will be discussed with reference to FIG. 7. FIG. 7 is a schematic diagram showing the arrangement of the bit lines and memory cells in a conventional semiconductor device.
For example, since a bit line BB1 neighbors bit lines BB0 and BB2, a coupling capacitance C10 is produced between the bit lines BB1 and BB0, and a coupling capacitance C12 is produced between the bit lines BB1 and BB0.
When both of the coupling capacitances C10 and C12 produced by the bit lines BB0 and BB2 is Cc, the total coupling capacitance CT between the bit line BB1 and the neighboring bit lines is 2xc3x97Cc based on the coupling capacitances C10 and C12 with the bit lines BB0 and BB2.
When the data output from a memory cell 100 in the SRAM to the bit line BB1 is the same as the data output from a memory cell 101 to the bit line BB2, the variations in electric potentials in the bit lines BB1 and BB2 are the same. Therefore, the coupling capacitance C12 between the bit lines BB1 and BB2 is estimated to be zero.
Under these conditions, which are the best conditions, the total coupling capacitance CT is reduced, the total coupling capacitance CT of the bit line BB1 is Cc based on the coupling capacitance C10 with the bit line BBO.
The worst condition to increase the total capacitance CT is that the data output from the memory cell 100 to the bit line BB1 is different from the data output from the memory cell 101 to the bit lines BB2. In this situation, variations in the electric potential in the bit lines BB1 and BB2 differ from each other.
In the worst condition, the total capacitance CT of the bit line BB1 is 2xc3x97Cc based on the coupling capacitances C10 and C12 with the bit lines BB0 and BB2.
As described above, when reading data from the SRAM, the access time may significantly differ, depending on the data output to the neighboring bit lines.
The actual access time when using the SRAM may be the above-described access time in the worst condition.
The total coupling capacitances between the bit lines may be averaged so that noise due to changes (loss) in data can be decreased when the data from the neighboring bit lines differ from each other. Thus, the access times under the best and worst conditions can be averaged, and the total access time can be shortened.
For the above-described reason, the twist bit line structure shown in FIG. 8 for decreasing the total coupling capacitance between the neighboring bit lines has been proposed. The twist bit line structure will be explained with reference to FIG. 7. FIG. 8 is a schematic diagram showing the arrangement of the twist bit lines and the memory cells in another conventional semiconductor device.
The memory cell array (memory cell area) 500 is divided into four blocks 501, 502, 503, and 504 having the same number of the memory cells (or the same number of word lines) in the direction of the bit lines (from the top to the bottom of the figure).
Blocks 251 are inserted between the first block 501 and the second block 502, and between the third block 503 and the fourth block 504. The blocks 251 exchange the bit line 221 with the bit line 222, and exchange the bit line 225 with the bit line 226. The bit lines 221 and 222 constitute a bit line pair, and the bit lines 225 and 226 constitute another bit line pair.
Similarly, a block 252 is inserted between the second block 502 and the third block 503. The block 252 exchanges the bit line 223 with the bit line 224, and exchanges the bit line 227 with the bit line 228. The bit lines 223 and 224 constitute a bit line pair, and the bit lines 227 and 228 constitute another bit line pair.
That is, the blocks 251 and 252 exchange the bit lines constituting bit line pairs.
As the result, in the arrangement of the bit lines in the SRAM shown in FIG. 8, there are five bit lines neighboring the bit line 224 which produce the coupling capacitances. That is, the bit line 224 neighbors the bit line 223 whish is one of the bit line pair, the bit lines 221 and 222 which constitute the bit line pair, and the bit lines 225 and 226 which constitute the other bit line pair.
Although the bit line 223 neighbors the bit line 224 in all the blocks 501 to 504, the bit line 223 neighbors the bit line 22 only in the block 501. Similarly, the bit line 223 neighbors the bit line 221 only in the block 502, neighbors the bit line 226 only in the block 503, and neighbors the bit line 225 only in the block 504.
That is, the bit line 223 neighbors one of the bit lines 221, 222, 225, and 226 in one of the blocks 501 to 504.
Whatever the memory cells 211, 212, and 213 output to the bit lines, the best and worst conditions for the read operation are averaged so that the total coupling capacitance of the bit line 223 can be equivalent to 3/2xc3x97Cc.
Because the bit line 223 always neighbors the bit line 224 which is one of the bit line pair, the coupling capacitance C34 between the bit lines 223 and 224 is always Cc.
Further, because the bit line 223 neighbors one of the bit lines 221, 222, 225, and 226 in one of the blocks 501 to 504, the capacitance value of zero under the best conditions and the capacitance value Cc under the worst conditions can be averaged.
Accordingly, the coupling capacitance between the bit line 223 and the bit lines 221, 222, 225, and 226 is 1/2xc3x97Cc.
The total coupling capacitance of the bit line 223 is 3/2xc3x97Cc regardless of the electric potentials of the data output from the memory cells 211 to 213 to the bit lines when reading the data.
As a result, as compared with the total coupling capacitance CT of 2xc3x97Cc under the worst conditions in the conventional bit line arrangement shown in FIG. 7, the bit line arrangement shown in FIG. 8 decreases the total coupling capacitances of the bit lines regardless of the electric potentials of the data output to the bit lines, thereby improving the access time to read the data.
However, in the twist bit line arrangement shown in FIG. 8, two bit lines constituting the bit line pair always neighbor each other. The two bit lines are complementary, and therefore always output different data. Therefore, the coupling capacitance Cc due to the worst conditions of the variation in the electric potentials is always present between the two bit lines constituting the bit line pair.
As described above, the conventional twist bit line arrangement in the conventional SRAM cannot decrease the total coupling capacitance between the bit lines to less than 3/2xc3x97Cc.
It is therefore an object of the present invention to provide a semiconductor memory device which can decrease the total coupling capacitance between the bit lines below 3/2xc3x97Cc, and which can accelerate the operation for reading data.
In the first aspect of the present invention, the semiconductor memory device comprises: memory cells arranged in a matrix; word lines extending in a row direction; bit line pairs extending in a column direction; exchange blocks for exchanging the bit lines of the different neighboring bit line pairs.
In the second aspect of the present invention, the semiconductor memory device according to claim 1 further comprises: memory cell blocks each of which has a predetermined number of the memory cells, and which are aligned in the column direction. The respective exchange blocks are positioned between the memory cell blocks.
In the third aspect of the present invention, first exchange blocks exchange the bit lines of the different neighboring bit line pairs, and second exchange blocks exchange the bit lines constituting the same bit line pairs. The first and second exchange blocks are arranged alternately.
In the fourth aspect of the present invention, the memory cells are divided into a plurality of memory cell blocks, the exchange blocks exchange the positions of the bit lines in the respective memory cell blocks so that each bit line neighbors the other bit lines only once in one of the memory cell blocks.
In the fifth aspect of the present invention, the semiconductor memory device further comprises: a first connection layer for forming the bit lines; and a second connection layer for exchanging the bit lines at the exchange blocks.
In the sixth aspect of the present invention, each bit line layer crosses one bit line at the exchange block.
In the seventh aspect of the present invention, each bit line layer crosses two bit line at the exchange block.
In the eighth aspect of the present invention, the respective bit line pairs are formed in the same connection layer outside the exchange blocks.
In the ninth aspect of the present invention, the respective bit line pairs are formed in a plurality of connection layers outside the exchange blocks.
A memory cell array is divided into the memory cell blocks, and the exchange blocks for exchanging the positions of the bit lines of the bit line pairs are inserted between the memory cell blocks, and exchange the positions of the bit lines of the same bit line pair and of different neighboring bit line pairs. Thus, the bit lines equally neighbors all the other bit lines. Therefore, regardless of the data values read from the memory cells to the bit line pairs, the total coupling capacitance between the neighboring bit lines is the average between the total coupling capacitance in the best data conditions of the neighboring bit lines and the total coupling capacitance in the worst condition, decreasing the cross-talk noise in the bit lines, and shortening the access time in the reading operation.
For example, when there are four bit line pairs, the total coupling capacitance CT with the neighboring bit lines is obtained by adding the coupling capacitance 1/4xc3x97Cc with the bit line constituting the bit line pair, the coupling capacitance 3/4xc3x97Cc with the bit lines which do not constitute the bit line pair, and the coupling capacitance 1/4xc3x97Cc with a bit line in another memory cell array, that is, 5/4xc3x97Cc.
The total coupling capacitance of the bit line and the neighboring bit lines is 5/4xc3x97Cc. As compared with the coupling capacitance {fraction (3/2)}xc3x97Cc between the bit lines in the conventional twist bit line method, the loads on the bit lines are significantly decreased. Therefore, the effect of cross talk noise between the neighboring bit lines can be reduced, and the access time for reading data from the memory cells can be shortened.
When the memory cell array has N bit line pairs, the coupling capacitance of each of the neighboring bit lines is ((N+1)/N)xc3x97Cc. As the number N of the bit line pairs is increased, and the total coupling capacitance of each of the neighboring bit lines can be brought close to Cc.
The total coupling capacitance between the neighboring bit lines is the average between the total coupling capacitance under the best data conditions of the neighboring bit lines and the total coupling capacitance under the worst condition, dispersing the effect of the cross-talk noise over the bit lines. Accordingly, the reading speeds are averaged between the bit line pairs, shortening the access time in the reading operation.